IC Layout Design Engineer

Job Overview

Job Description

3 Layout positions below

1) Mixed-Signal IC Layout Lead
Richardson, Texas (onsite/hybrid)
US Citizen or US Permanent Resident

Responsibilities:
• Chip-level integration including IP blocks, digital blocks, and analog blocks
• Chip-level verification including DRC/LVS/EMIR, parasitic extraction, and metal density fill

Required Experience:
• 10+ years industry experience in IC layout
• Solid experience in Cadence Virtuoso/Synopsys Custom Compiler Layout tool and verification tools, Calibre/PVS/IC Validator
• Experience in LVS and DRC
• Good understanding of the semiconductor foundry process flow
• BSEE or Associate of Applied Science (ASS) degree in IC Layout Design
• Strong communication and customer service skills, ability to work under time constraints, attention to details, reading layout specifications

2) RF Layout Design Engineer
Richardson, Texas (onsite/hybrid)
US Citizen or US Permanent Resident

Required Experience:
• 5 years of industry Experience
• FinFET experience
• High proficiency in interpreting CALIBRE DRC, ERC, and LVS
• Proficient with CADENCE layout tools
• Strong background in custom RF/analog layout for transceivers and deep sub-micron CMOS technologies

Preferred Experience:
• Experience with advanced nodes (7nm and below)
• Knowledge of guard rings, DNW, PN junctions, and advanced process effects (LOD, WPE, etc.)
• Skilled in layout techniques for device matching, parasitic reduction, RF shielding, and high-frequency routing
• Solid understanding of RC delay, electromigration, and signal coupling
• Strong communication skills and ability to collaborate with designers and layout teams

3) IC Layout Designer
Richardson, Texas (onsite/hybrid)
US Citizen or US Permanent Resident

Requirements:
• 3+ years of experience in Cadence layout (Virtuoso, VXL) and Calibre verification (ERC, DRC, LVS)
• 3+ years of experience in layout and verification tools and methodologies for RF/Analog/Mixed-Signal ICs
• BSEE or AA degree
• FinFET is preferred
• Comprehensive understanding of matching, shielding, guard rings and latch up
• Debugging and analytical skills with complex technical concepts
• Demonstrated success in delivering quality work product
• Experience in DFM hierarchical layout construction for efficient verification and integration
• Must understand techniques for managing layout dependent effects i.e. IR drop, RC delay, electron-migration, self- heating and crosstalk
• Proficiency in PERL or SKILL scripting is a plus
• Strong verbal and written communication

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Javier Leon
FJLrecruiter @ gmail.com